1. Field of the Invention
The present invention relates to a memory access controller used in portable devices, such as mobile phones, digital cameras, and so on, and more specifically, to a memory access controller having high data transmission efficiency.
2. Description of the Related Art
There is increasing demand for portable devices, such as mobile phones, video cameras, digital cameras, and so on. Such devices perform a variety of types of data processing, achieved by large-scale integration (LSI) circuits (hereinafter simply “LSIs”). For example, video cameras and digital cameras include specific LSIs that process image data captured from an image sensor of the digital camera. Further, mobile phones and other such portable devices include other specific LSIs that process audio data in different ways. Such LSIs that perform complex processing of large volumes of data are required to have high throughput in data transmission to an attached storage device such as a memory. To satisfy such requirements, a variety of related technologies have been researched and developed.
JP-2008-165485-A proposes a semiconductor device to perform data transmission on data stored in a buffer efficiently. The semiconductor device includes a data processing unit for processing a plurality of data, a buffer for temporarily storing and burst-transferring the data processed by the data processing unit, and a buffer control unit for causing the buffer to burst-transfer the stored data. The buffer control unit causes the buffer to start the burst transfer so that data to be stored in the buffer from the data processing unit will not be replaced before a data amount to be transferred in a single burst transfer is stored in the buffer.
However, this semiconductor device is intended simply to improve efficiency of data transmission from the buffer to an arbitration circuit without considering processing performed in a memory controller to which the data is transmitted.
JP-2006-127408-A proposes another data transmission system. The data transmission system includes a plurality of masters, a memory controller, and a bus arbiter. The memory controller controls an external memory. The bus arbiter arbitrates bus use requests from the bus masters.
The memory controller notifies each bus master of bus use recommendation information, and each bus master issues a bus use request to the bus arbiter based on the bus use recommendation information reported from the memory controller.
FIG. 1 is a block diagram of a DRAM controller 100 which a plurality of bus masters 301, 302, and 303 access. A command I/F is connected to the DRAM controller 100 to input data such as address read/write through the command I/F to a DRAM 200 from the bus masters 301, 302, and 303. Further, a data I/F is connected to the DRAM controller 100 to input data such as write data through the data I/F. Furthermore, the DRAM controller 100 includes a command analysis unit 101 and a command execution unit 102. The command analysis unit 101 determines command input data to be issued to the DRAM 200 based on the input data from the command I/F representing read, write, number of accesses, and address. The command execution unit 102 receives the command input data analyzed by the command analysis unit 101 and data input through the data I/F and controls timing for outputting a command control signal and a data control signal to the DRAM 200. The DRAM 200 is a memory which can perform burst-transferring, for example, a Synchronous Dynamic Random Access Memory (SDRAM), a Double-Data-Rate (DDR)-SDRAM, or the like.
In the DRAM controller 100, a latency between when the data is input through the command I/F and when the data is output to the DRAM 200 as the command control signal is larger than a latency between when the data is input through the data I/F and when the data is output to the DRAM 200 as the data control signal. This is because more jobs are performed on the data input through the command I/F than the data input through the data I/F, for example, analyzing signals input from the command I/F and generating a plurality of commands, or determining processing by read/write.
Accordingly, even when the data are input to the command I/F and the data I/F at the same time, it is not possible to output the data input from the data I/F to the DRAM 200 as the data control signal for the DRAM 200 until data transmission for the data input from the command I/F is completed. Further, it is not possible for the DRAM controller 100 to access the DRAM 200. As a result, transmission efficiency between the DRAM controller 100 and the DRAM 200 is decreased.
In the system shown in FIG. 1, the plurality of bus masters 301, 302, and 303 is connected to the DRAM controller 100 through a command I/F and a data I/F. Accordingly, one bus master occupies a bus for the command I/F and a bus for the data I/F. For example, when the bus master 301 issues a write request to the DRAM controller 100 through the command I/F, the other bus masters 302 and 303 cannot send a write request to the DRAM controller 100 until completion of the data input through the data I/F.
Thus, during such a large latency between when a bus master issues a write request and when preparation of data to be input to the data I/F is finished as described above, the command I/F and the data I/F are occupied. Accordingly, the other bus masters cannot send a write request, and consequently, transmission efficiency of the DRAM controller 100 for the DRAM 200 is decreased.